Title:
半導体ウェーハの蝕刻状態計測方法
Document Type and Number:
Japanese Patent JP4159734
Kind Code:
B2
Abstract:
Embodiments of the present invention include methods for measuring a semiconductor wafer which has been subjected to an etching process. Light is radiated at the semiconductor wafer. Light within a selected wavelength band reflected from the semiconductor wafer is measured to provide an output value. A ratio of the output value and a reference value is determined. The reference value may be based on light within the selected wavelength band reflected from a reference surface, such as a bare silicon reference surface. It is determined that the semiconductor wafer is under-etched if the determined ratio does not meet the reference value. A normalized optical impedance or a polarization ratio may be measured based on light within a selected wave length band reflected from the semiconductor wafer to provide the output value in various embodiments of the present invention. In further aspects of the present invention, a thickness of a remaining oxide layer is determined using an under-etch recipe when it is determined that a semiconductor wafer is under-etched and a thickness of a damaged/polymer layer may be determined using an over-etch recipe when it is determined that the semiconductor wafer is over-etched.
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Inventors:
Zhao large
Full phase
Choi
All Tadamori
Ginger Agility
Full phase
Choi
All Tadamori
Ginger Agility
Application Number:
JP2000276271A
Publication Date:
October 01, 2008
Filing Date:
September 12, 2000
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G01B11/06; H01L21/3065; H01L21/302; H01L21/66
Domestic Patent References:
| JP5259127A | ||||
| JP4176145A | ||||
| JP11087448A | ||||
| JP2000031226A | ||||
| JP63082348A |
Attorney, Agent or Firm:
Masaki Hattori