Title:
累乗演算装置
Document Type and Number:
Japanese Patent JP4274633
Kind Code:
B2
Abstract:
The device performs an exponentiation operation on an input base bit sequence and on an input exponent bit sequence with a logarithmic operation unit (2), a multiplier (1), a bit operation unit (5), an exponent check unit (4), a multiplication bit sequence selection unit (6) and an exponential operation unit (7).
Inventors:
Yoshitsugu Inoue
Hiroyuki Kawai
Junko Ohara
Robert Striteenberger
Keisuke Yoshimatsu
Hiroyasu Negishi
Hiroyuki Kawai
Junko Ohara
Robert Striteenberger
Keisuke Yoshimatsu
Hiroyasu Negishi
Application Number:
JP17736899A
Publication Date:
June 10, 2009
Filing Date:
June 23, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F7/552; G06F7/556
Domestic Patent References:
| JP10510383A | ||||
| JP62257529A | ||||
| JP5250146A |
Other References:
井上喜嗣 外8名,3次元グラフィックス向け浮動小数点累乗演算器の開発,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,1999年 6月24日,Vol.99 No.145,p17-22
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa