Title:
FABRICATION OF COMPLEMENTARY N-CHANNEL AND P-CHANNEL INTEGRATE CIRCUIT USEFUL FOR MANUFACTURING OF DYNAMIC RANDOM ACCESS MEMORY
Document Type and Number:
Japanese Patent JPH05259400
Kind Code:
A
Abstract:
PURPOSE: To provide a method for fabricating n-channel and p-channel metal oxide semiconductor devices which are useful in the manufacturing of an extremely large-scale integrated circuit, e.g. a high-density DRAM. CONSTITUTION: First, n-channel and p-channel gate layers of selected conductive and nonconductive materials 14, 22, 24, 26 are formed on the surface of semiconductor substrates 10, 12. A memory array and the n-channel gate layer of the circumferential part on a substrate are formed optically at first, and the p- channel gate layer is left at a predetermined position in an area 12 on the substrate where a p-channel transistor and a p<+> -active region are formed. Subsequently, a series of ion-implantation steps are executed, in order to form an n-channel transiting without requiring a masking step. The gate layer at a specified position on the periphery of the p-channel serves as a mark at the time of ion-implantation to the peripheral part, thus preventing n-type ions from flowing into the peripheral p-type transistor region.
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Inventors:
Charles H. Denison
Tyler A. Lowry
Tyler A. Lowry
Application Number:
JP30329892A
Publication Date:
October 08, 1993
Filing Date:
October 16, 1992
Export Citation:
Assignee:
MICRON TECHNOLOGY,INCORPORATED
International Classes:
H01L21/8238; H01L21/8242; H01L27/092; H01L27/10; H01L27/108; H01L27/105; (IPC1-7): H01L27/092; H01L27/108
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)