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Title:
FAIL-FIRST, FAIL-FUNCTIONAL AND FAULT TOLERANT MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPH09244960
Kind Code:
A
Abstract:

To check the error of a processor at an interface spot without affecting the processor performance by providing a specific table means and also a means which receives a message from a peripheral device and decides whether the access should be permitted to a memory means based on the received message.

The routers 14A and 14B are connected to the subprocessor systems 10A and 10B, and the I/O packets 16A and 16B are connected to the routers 14A and 14B respectively. This device of such a constitution has a table means which includes plural entries to discriminate permission of the access to a part of a memory means against one of its peripheral devices. Therefore, the message packet sent via an I/O has the information on the originator and the destination. Then a receiving CPU refers to the external source that is permitted to access its memory via an access propriety check and a conversion (AVT) table and checks whether the access is permitted or not.


Inventors:
ROBAATO DABURIYUU HOOSUTO
UIRIAMU EDOWAADO BEIKAA
UIRIAMU PATAASON BANTON
GEARII EFU KIYANBERU
RICHIYAADO DABURIYUU KATSUTSU
DANIERU ERU FUAURAA
DEIBUITSUDO JIEI GAASHIA
POORU ENU HINTEITSUKA
JIEFURII AI ISUWANDEII
DEIBUITSUDO POORU SOONIA
UIRIAMU JIYOERU WATOSON
FURANKU EI UIRIAMUSU
Application Number:
JP14605796A
Publication Date:
September 19, 1997
Filing Date:
June 07, 1996
Export Citation:
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Assignee:
TANDEM COMPUTERS INC
International Classes:
G06F12/14; G06F11/18; G06F15/16; G06F15/163; G06F15/167; (IPC1-7): G06F12/14; G06F15/16; G06F15/163
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)



 
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