To detect a failure at high speed with high reliability by a distributed memory-I/O configuration and a common memory-I/O configuration by practically using compression information.
This failure detection device includes: a plurality of arithmetic processors; distributed memories-I/Os by the use of which the arithmetic processors perform the input/output of information; and a plurality of comparison compression means connected to the arithmetic processors and the distributed memory-I/O, respectively. The plurality of comparison compression means compress information exchanged by the arithmetic processors and the distributed memories-I/Os, and exchange and compare the compressed information between the plurality of comparison compression means. When a comparison result indicates discordance, the failure detection device decides that one or all of the plurality of arithmetic processors fail.
| JP2006178618A | 2006-07-06 | |||
| JPH0683663A | 1994-03-25 | |||
| JPH08212093A | 1996-08-20 | |||
| JP2005165807A | 2005-06-23 | |||
| JPH05324391A | 1993-12-07 | |||
| JP2008146447A | 2008-06-26 |
Masao Sekiguchi
Takamasa Nakano