Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FAILURE MONITOR DEVICE FOR POWER CONVERTER
Document Type and Number:
Japanese Patent JP3303104
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To shorten the tracing time of the cause of the failure of a switching element largely by stopping the update of monitor data and reproducing the data when a failure accident occurs.
SOLUTION: When a microcomputer 21 is accessed to a specified address and a signal is outputted from an address decoder 17, a monitor start/stop register 15 outputs a monitor start signal, and clock pulses having a period sufficiently shorter than monitored gate pulse width are outputted to latches 11, 12 from a clock generator 14. The latch 11 holds the on-off state at a time of current sampling and the latch 12 holds it at a time of previous sampling and outputs from both latches are inputted to a comparator 13, and an address counter 18 is operated and the output from the latch 11 and the time data of a time counter 19 at that time are stored in an address at a page address + address counter value when both outputs do not coincide, and the monitor is continued. Accordingly, the time of the tracing of a cause can be shortened largely.


Inventors:
Naohiro Ikeda
Eiichi Toyoda
Naoki Kusano
Mutsuhiro Terunuma
Hideo Sakuyama
Application Number:
JP12651696A
Publication Date:
July 15, 2002
Filing Date:
April 23, 1996
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
株式会社日立製作所
International Classes:
H02M1/00; H02M7/48; H02P27/06; H03K5/1532; H03K7/08; (IPC1-7): H02M7/48; H02M1/00; H02P7/63; H03K5/1532; H03K7/08
Domestic Patent References:
JP6169575A
JP5236763A
JP614558A
JP6153510A
JP54783U
Attorney, Agent or Firm:
Shigeru Sasaoka (1 person outside)



 
Previous Patent: STONE DRAWING ANCHOR

Next Patent: PROCESS INPUT/OUTPUT DEVICE