Title:
LEVEL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3130791
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To convert a signal of an ECL(emitter coupled logic) level into a MOS level signal with a low power supply voltage by giving an output of a differential amplifier to a CMOS(complimentary MOS) inverter via a logic level amplifier circuit.
SOLUTION: A bipolar differential amplifier is made up of transistors(TRs) Q1, Q2 of a differential pair using resistors R1, R2 as loads and receiving ECL level inputs IN, INB respectively and up of a constant current source IDDI. Furthermore, A logic level amplifier circuit is made up of a current mirror circuit consisting of a TR Q3 whose collector and base connects to a collector of the TR Q2 being a node A of the bipolar differential amplifier and whose emitter connects to ground and consisting of a TR Q4 acting like a current source whose emitter connects to ground and whose base connects to the base of the TR Q3, and up of a resistor R3 whose one terminal connects to a power supply and whose other terminal connects to the collector of the TR Q4 being a node B. A CMOS inverter whose input, connects to the collector of the TR Q4 provides an output of a CMOS level to a node OUT.
Inventors:
Masato Nishikawa
Application Number:
JP7505396A
Publication Date:
January 31, 2001
Filing Date:
March 29, 1996
Export Citation:
Assignee:
NEC
International Classes:
H03K19/086; H03F3/45; H03K19/0175; (IPC1-7): H03K19/0175; H03F3/45; H03K19/086
Domestic Patent References:
| JP4172713A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)