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Title:
FAULT BLOCK DETERMINATION SYSTEM, SCRAMBLER, DESCRAMBLER, AND DIGITAL SIGNAL PATTERN GENERATOR
Document Type and Number:
Japanese Patent JP2005117607
Kind Code:
A
Abstract:

To provide a system for determining a fault block on a digital line from an input signal and an output signal of one device arranged on the line in the case of line fault without affecting communication between users at an ordinary time.

In the fault block determination system, a scrambler and a descrambler are arranged on the relevant line, the scrambler has a polynomial for scrambling a series of "0" and a series of "1" to any series other than "1" independently of a status of a shift register and when an input signal of the descrambler is a series of "1", it is determined that a fault block exists between the scrambler and the descrambler. When an output signal of the descrambler is a series of "1", it is determined that a fault block exists far from the scrambler.


Inventors:
KATAOKA MASATO
Application Number:
JP2004002615A
Publication Date:
April 28, 2005
Filing Date:
January 08, 2004
Export Citation:
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Assignee:
KATAOKA MASATO
International Classes:
H04L69/40; H04L9/20; (IPC1-7): H04L29/14; H04L9/20
Attorney, Agent or Firm:
Yasuo Ishikawa