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Title:
FAULT END CONTROL SYSTEM UNDER FAULT END PROCESSING
Document Type and Number:
Japanese Patent JPS607541
Kind Code:
A
Abstract:

PURPOSE: To promote debugging by skipping the block where a fault end phenomenon is produced during fault end processing to carry out the processing up to the final block and deciding the factor of the first fault end.

CONSTITUTION: When a fault end phenomenon arises, control is delivered to an OS and then to an FORTRAN library designated as an outlet routine. Then a fault end processing module is loaded to register the fault end outlet in preparation for a fact that a fault end is given again during the fault end processing. The processing block is executed after calling out a control routine, and the processing is continued up to the last block. If a fault end phenomenon arises at the middle of processing, control is handed to the outlet registered at a fault end processing control part 4. The fault end outlet is registered again in preparation for the second occurrence of the fault end phenomenon. Then the occurring frequencies are counted for the fault end, and an endless loop of the processing is avoided.


Inventors:
HORIGUCHI HIROKAZU
Application Number:
JP11561583A
Publication Date:
January 16, 1985
Filing Date:
June 27, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/00; G06F9/06; G06F11/36; (IPC1-7): G06F11/00; G06F9/42
Attorney, Agent or Firm:
Kyotani Shiro



 
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