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Patent Searching and Data


Title:
FET AMPLIFIER
Document Type and Number:
Japanese Patent JP2003078358
Kind Code:
A
Abstract:

To obtain an FET amplifier which can compensate for more effectively temperature fluctuation of gain of an FET.

Instead of a drain bias resistor, n (a positive integer) silicon diodes X1-Xn connected in series are inserted in a part between a drain electrode of the FET 6 and a positive voltage supply terminal. Only the temperature fluctuation of each forward direction voltage of the silicon diodes X1-Xn is used and a drain voltage and a drain current of the FET are changed, thereby compensating the gain of the FET. Differently from the case that the drain bias resistor is used, the drain voltage can be prevented from changing dependently on the change of a drain current, so that it can be restrained to apply limit to the amount of compensation of gain of the FET.


Inventors:
SAKAKI SHINICHI
Application Number:
JP2001269618A
Publication Date:
March 14, 2003
Filing Date:
September 06, 2001
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
H03F1/30; H03F3/193; (IPC1-7): H03F1/30; H03F3/193
Attorney, Agent or Firm:
Yanagi Kawa Shin