To provide a field-effect transistor having a T-shaped gate electrode, together with its manufacturing method which has a reduced source resistance, a reduced gate resistance, and a reduced gate capacitance while keeping a sufficient gate breakdown voltage, and which can be manufactured with high accuracy and a high yield.
A first doped layer 6 of n-GaAs, a side-etching prevention layer 7 of Al0.22Ga0.78As, and a second doped layer 8 of n-GaAs, are sequentially grown on a layer 5 of n-Al0.22Ga0.78As. A recess is formed in a central region of the second doped layer 8, the side-etching prevention layer 7 and the first doped layer 6, so as to expose the layer 5 of n-Al0.22Ga0.78As there. On the exposed layer 5 of n-Al0.22Ga0.78As in the recess, a T-shaped gate electrode is formed. The etching rate of the side-etching pretension layer 7 is smaller than those of the first and the second doped layers 6 and 8.
TOMINAGA HISAAKI
Next Patent: SUBSTRATE FOR MOUNTING SEMICONDUCTOR DEVICE