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Title:
FIFO MEMORY
Document Type and Number:
Japanese Patent JPS6458015
Kind Code:
A
Abstract:

PURPOSE: To obtain a CMOS type first-in first-out FIFO memory by carrying out the FIFO of data via the circulating count-up of both push and pop addresses in place of the transfer of the pushed data itself.

CONSTITUTION: The 8-bit data D is written into a push address which is designated by the 5-bit count value of a counted-up push address counter 12 at a time point when an enable signal IR' is turned on and a clock signal PL has a rise. While the stored 8-bit data is read out of a pop address which is designated by the 5-bit count value of a counted-up pop address counter 13 at a time point when an enable signal OR is turned on and the signal PL has a fall. The read- out data is sent to the next stage as an output Q. An address difference arithmetic circuit 14 holds the difference between the count value of the counter 12 and that of the counter 13. Then the signal IR' is set at zero when the difference of both addresses is equal to 32.


Inventors:
OKAWA KENZO
Application Number:
JP21491987A
Publication Date:
March 06, 1989
Filing Date:
August 28, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F5/06; G06F9/22; G06F9/26; G11C7/00; (IPC1-7): G06F5/06; G06F9/26; G11C7/00