To provide a flash memory controller which can be mounted on a memory interface of a host computer.

A buffer 9 of a controller 3 is used for data exchange operation between the host computer 4 and the controller 3, and data exchange operation between a flash memory 2 and the controller 3. A host interface control block 5 as a first control block controls data exchange operation between the buffer 9 and the host computer 4. A flash sequencer block 12 as a second control block controls data exchange operation between the buffer 9 and the flash memory 2. The host interface control block 5 controls input and output operation of the buffer 9 based on information from the host computer 4. The flash sequencer block 12 controls input and output operation of the buffer 9 at a one-page size space of the flash memory 2.