FLASH MEMORY AND MANUFACTURE THEREOF

Japanese Patent JP3783240

B2

PURPOSE: To eliminate the deterioration of the transistor characteristics even if an interval of word lines is reduced and to reduce a transistor pattern by forming the thickness of a gate electrode the same as that of a field insulating film, once covering it with a CVD insulating film, and forming a sidewall on the sidewall of the electrode.
CONSTITUTION: After a gate electrode 4 is formed substantially in the same thickness as that of a field insulating film 2 of a semiconductor substrate 1 in an active region demarcated by the film 2, the region except a drain region between the electrodes 4 on the substrate 1 is covered with a drain diffusion footing resist film 5 to form a drain diffused layer 6 in the substrate 1. Then, it is so covered with a CVD insulating film 7 as to coat at least the active region of the surface of the substrate 1, and a sidewall is formed on the sidewall of the electrode 4. The film 7 on the drain region is covered with an insulating film etching resist film 8, and the film 7 and the film 2 of the source region are removed by etching.

JP3732524	Manufacturing method of integrated semiconductor memory device
WO/2001/071803	A DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
JPS5671978	PREPARATION METHOD OF SEMICONDUCTOR SYSTEM

Kazuaki Yamanouchi

JP22327094A

June 07, 2006

September 19, 1994

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富士通株式会社

H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L29/788; H01L29/792; H01L27/115

JP2065275A
JP3290960A
JP2177478A
JP2181971A

Junichi Yokoyama

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