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Title:
FORMATION OF CONTACT BETWEEN INTERCONNECTIONS
Document Type and Number:
Japanese Patent JPS6411345
Kind Code:
A
Abstract:

PURPOSE: To suppress contact resistance between the first and second interconnections so that it becomes sufficiently small by removing the surface of the first conductor interconnection up to a prescribed depth after performing a process wherein a through hole is formed and then, by forming thin films for use in the second conductor interconnection in multilayer interconnections.

CONSTITUTION: In a state where a semiconductor substrate 1, a SiO2 film A2, the first Al interconnection 3, a SiO2 film B4, a photoresist film 5, a through hole 6, and a high resistance layer 7 are formed, reactive ion etching is carried out with a SiCl4 gas. Its treatment is performed on condition that an Al film of only about 0.1μm is etched. In this way, a part of about 0.1μm thick at the surface of a contact part of the first Al interconnection 3 is removed. (it is shown as an Al removal part 8). Then an aluminum metallic film is deposited in the same way that found conventionally and the second Al film 9 is formed. Thus, the high resistance layer 7 which has been formed at the surface of the contact part of the first Al interconnection 3 is removed together with the Al removal part 8 and the first Al interconnection 3 is connected with the second part Al film 9 at the part of the through hole 6 and then contact resistance between the above two parts can be suppressed so that it may become sufficiently small without exception.


Inventors:
IMAI HIROSHI
KUBOTA MASABUMI
Application Number:
JP16719187A
Publication Date:
January 13, 1989
Filing Date:
July 03, 1987
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L23/522; H01L21/768; (IPC1-7): H01L21/90
Attorney, Agent or Firm:
Toshio Nakao



 
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