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Patent Searching and Data


Title:
FORMATION OF GATE ELECTRODE
Document Type and Number:
Japanese Patent JPH11214407
Kind Code:
A
Abstract:

To provide a method for forming a gate electrode of a semiconductor device, in which a sophisticated mask aligning process is not used, and damage to and deformation of the gate electrode are prevented, by forming dummy photoresist layers on the semiconductor substrate in the lift-off process to make the position of the substrate surface higher than the top end of the gate electrode.

On a semiconductor substrate 1, photoresist layers having an opening are formed, and after evaporating a metal layer 3 on the whole surface, the metal layer 3 that is on the photoresist layers is lifted off while the metal layer 3 remaining directly on the semiconductor substrate 1 is used as a gate electrode 3', wherein the photoresist layers are constituted by a lower-lying photoresist layer 8 and an upper-lying photoresist layer 9 stacked on the lower- lying photoresist layer 8 so that the position of the top surface of the photoresist layers is made higher than that of the top surface of the gate electrode 3'. In the lift-off process, the metal layer 3 that is on the upper-lying photoresist layer 9 is lifted off, wherein only the upper-lying photoresist layer 9 is solved selectively while the lower-lying photoresist layer 8 remains to protect the gate electrode 3'.


Inventors:
TOTSUKA MASAHIRO
MATSUOKA TAKASHI
OKU YUUKI
Application Number:
JP1681698A
Publication Date:
August 06, 1999
Filing Date:
January 29, 1998
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/28; H01L21/338; H01L29/812; (IPC1-7): H01L21/338; H01L21/28; H01L29/812
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)