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Title:
FORMING METHOD FOR TWISTED MULTILAYER INTERCONNECTIONS OF SEMICONDUCTOR DEVICE OR THE LIKE
Document Type and Number:
Japanese Patent JPH06132622
Kind Code:
A
Abstract:

PURPOSE: To enhance wiring density by twisting interconnections of upper and lower layers via in-line or concentrated holes.

CONSTITUTION: A left interconnection A of an upper wiring layer 2 is connected with a central interconnection A of a lower wiring layer 3 via holes 1 provided between right ends and the left ends of the central interconnection A. Further, the central interconnection A is connected with the left interconnection A via holes 1 provided between the right lower ends and a left lower end of the right interconnection A. Similarly, a left interconnection B the wiring layer 3 is connected with a central interconnection B of the wiring layer 2, and the central interconnection B 2 is connected with a right interconnection B of the wiring layer 3 via the holes 1 provided at predetermined positions of the interconnections. In this case, the wiring layers 2, 3 are twisted between the upper and lower layers.


Inventors:
NAKADA KENSUKE
MISHIMAGI HIROMITSU
Application Number:
JP28137292A
Publication Date:
May 13, 1994
Filing Date:
October 20, 1992
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/413; H01L21/768; H01L23/522; H05K1/11; H05K3/46; H05K1/02; (IPC1-7): H05K1/11; G11C11/413; H01L21/90; H05K3/46
Attorney, Agent or Firm:
Ogawa Katsuo