Title:
FORMING METHOD OF WIRING LAYER
Document Type and Number:
Japanese Patent JPS56138941
Kind Code:
A
Abstract:
PURPOSE:To improve the pattern accuracy of a wiring layer and protect the wiring layer against corrosion by utilizing an insulating layer for patterning the wiring layer. CONSTITUTION:An aluminum alloy film 10 is covered by evaporation through an insulating film 2 formed on the surface of a semiconductor substrate 1, a silicon nitride film (or a silicon oxide film) 11 is covered thereon, and a mask of a resist film 12 is formed thereon. Then, the film 11 is etched and removed for patterning. Thereafter, with the films 12 and 11 as masks the film 10 is reactively ion etched to pattern the wiring layer. Thereafter, when the film 12 is molten and removed, a wiring layer made of the film 10 covered with the silicon nitride film is formed. Thus, the resist film becomes sufficient only with half a thickness of the conventional one to improve the pattern accuracy of the wiring layer.
Inventors:
TOKITOMO KAZUO
TAKADA CHIYUUICHI
TAKADA CHIYUUICHI
Application Number:
JP4175380A
Publication Date:
October 29, 1981
Filing Date:
March 31, 1980
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/302; H01L21/3065; H01L21/3213; (IPC1-7): H01L21/302