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Title:
FRAME SIGNAL FEEDBACK LOOP CIRCUIT
Document Type and Number:
Japanese Patent JPH06334640
Kind Code:
A
Abstract:

PURPOSE: To improve reliability without issuing an unnecessary alarm by providing a circuit transmitting prescribed data as a data signal for a period when a frame signal is made a feedback loop state between a device side loop back setting part and an F-CONV, and preventing the state from becoming a pseudo synchronizing state.

CONSTITUTION: Each transmission line I/F terminal part of a terminal station device duplexed by an operational system and a non-operational system is composed of a transmission line, a device-side loop back setting parts 1 and 2, a terminal part 4 and an F-CONV part 5. In the non-operational system, the setting part 1, the terminal part 4, the setting part 2 and the F-CONV part 5 are defined as circuits where frame signals are made feedback loop states in this order. A data/status and mask setting part 6 is added between this setting part 2 and the CONV part 5, and prescribed data as data signals is transmitted for a period when the setting part 6 makes the frame signals the feedback loop states. Thus, the monitoring is surely performed by preventing the state from by being a pseudo synchronizing state in the execution of the self- monitoring in non-operation to improve the reliability issuing without giving an unnecessary alarm at the time of setting the operational state, etc.


Inventors:
IKUI YUICHI
KODACHI HIRONORI
OTSUKA MASANORI
Application Number:
JP11748693A
Publication Date:
December 02, 1994
Filing Date:
May 20, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B1/74; H04L7/00; H04L7/08; H04L69/40; (IPC1-7): H04L7/00; H04B1/74; H04L7/08; H04L29/14
Attorney, Agent or Firm:
Teiichi