PURPOSE: To attain high speed processing by preparing plural kinds of frame synchronizing signals for digital signals of frame constitution so as to facilitate the decoding of a time diversity.

CONSTITUTION: The transmission signal series to be sent is sent twice each while being separated into frames, a 1st frame synchronizing signal FA is added to the 1st frame and a 2nd frame synchronizing signal FB is added to the 2nd frame. The 1st frame synchronizing detection circuit 24 outputs an enable signal 29 when the 1st frame synchronizing signal pattern is detected. The enable signal 29 is given to the 2nd frame synchronizing detection circuit 25. After receiving the enable signal 29, the 2nd frame synchronizing detection circuit 25 awaits the processing by a delay bit number of the time diversity and compares the signal patterns of he reception signal and the 2nd frame synchronizing signal. The decoding procedure of the time diversity is simplified in this way to attain high speed decoding.