FREQUENCY CONTROL METHOD AND INFORMATION PROCESSOR

Title:

FREQUENCY CONTROL METHOD AND INFORMATION PROCESSOR

Document Type and Number:

Japanese Patent JP2005182473

Kind Code:

A

Abstract:

To efficiently suppress waste of driving power without lowering the processing speed of a CPU more than necessary.

Every time processing through an OS is performed, the value of a clock frequency suitable for a load of the processing is calculated. Then, prior to rewriting of the clock frequency managed at a CPU register 1a, data on the upper limit value of the clock frequency calculated in accordance with the level of power savings specified by a user in advance is read from a BIOS-ROM 6, and this value is compared with the value of the clock frequency calculated in accordance with the type of processing of the OS to determine which is lower. The value determined as lower is written on the CPU register 1a to control the operating frequency of the CPU 1.

Inventors:

SANADA TOSHITAKA

Application Number:

JP2003422549A

Publication Date:

July 07, 2005

Filing Date:

December 19, 2003

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

G06F1/04; G06F1/32; (IPC1-7): G06F1/04

Attorney, Agent or Firm:

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto

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