Title:
FULL ADDER
Document Type and Number:
Japanese Patent JPH04230520
Kind Code:
A
Abstract:
PURPOSE: To enable high-speed multistage addition by shortening delay time for operation.
CONSTITUTION: Addition bits i1, i2, and i3 and 6 bits with their logic NOT are inputted. A sum (s) is obtained by exclusive OR circuits mpx1 and mpx2. The logic NOT of the sum (s) is obtained by the negative exclusive OR circuits mpx3 and mpx4. Carry (c) and their logic NOT are obtained respectively by the carry operation circuits cgen1 and cgen2. Thus obtained sum (s), carry (c), and their logic NOT are outputted.
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Inventors:
HIRASAWA MASAO
HARADA KANJI
HARADA KANJI
Application Number:
JP41720090A
Publication Date:
August 19, 1992
Filing Date:
December 29, 1990
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F7/501; G06F7/50; G06F7/503; G06F7/506; (IPC1-7): G06F7/50
Attorney, Agent or Firm:
Masanori Fujimaki