Title:
FUNCTIONAL TRANSFORMATION ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP3727406
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize speedy butterfly arithmetic by parallel processing by constituting a functional transformation arithmetic unit such as FFT(fast Fourier transform) through the use of an analog circuit and replacing the order of the arrangement of an output signal group with a prescribed one.
SOLUTION: A butterfly arithmetic circuit executing prescribed functional transformation such as FFT to a functional transformation arithmetic circuit part 5 is constituted of an adder 2, a subtracter 3 and multipliers 4-0 to 4-3. An inputted analog signal group (a) is transformed to parallel discrete signal groups x0 to X7 by an analog serial-parallel transformation circuit part 1 to supply for each input terminal of the butterfly arithmetic circuit and signal groups X0 to X7 obtained from each output terminals of the butterfly arithmetic circuit are switch-processed by a switch circuit part 6 to transform a serial signal group (f). The switching operation of this switching circuit part 6 is controlled based on a sequence previously set by a control part 7 and each signal group is transformed to the serial signal group (f) lined up in the order of X0 to X7.
Inventors:
Nobuaki Kawahara
Kenzo Urabe
Zhou Chomei
Kotobuki Kokuryo
Kenzo Urabe
Zhou Chomei
Kotobuki Kokuryo
Application Number:
JP7947296A
Publication Date:
December 14, 2005
Filing Date:
March 07, 1996
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
G06G7/19; (IPC1-7): G06G7/19
Domestic Patent References:
| JP63121311A | ||||
| JP59205670A | ||||
| JP58127239A |
Attorney, Agent or Firm:
Tatsuo Moriyama