To provide an adder of binary gate 3.7 stages or 3 stages.

While it can be an optional digit, in the example of four digits, the AND(1) carry C=H signal of 1 digit is put in a C41 line (2) → a diode di (3) → an intersection p(4) → a 4-digit AND gate E1 (5), E0(6) and a NOR gate N(7), the output of the E1, E0 and N is put into an OR gate R(8), the C=H signal is simultaneously put through the di(9) into the base b(11) of a transistor TR(10) and the b is connected through a resistor r(12) to the ground. 00, L signals prepared in the OR(13) of intermediate 2-3 digits are put through the di(14) to the C41 line and the output of the AND(15) is put into the E1 and N above and the output of the NOR(16) is put into the E0 and N above. The TR(17) is put in the fourth input line n of the N, the base of the TR(17) is connected with the base of the TR(10), the input line n is turned to H until H signals come to the point p and thus, the error that the N(7) outputs a sum is prevented.