Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
GATE ARRAY SYSTEM SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS63177395
Kind Code:
A
Abstract:

PURPOSE: To set a storage circuit as a RAM or a ROM by constituting the storage circuit with an FF, a couple of bit lines and a gate element which is connected to a respective bit lines and to either the FF or an earth.

CONSTITUTION: The FF consists of MOSFETs 101W104 in a memory cell. The bit lines 113 and 114 are connected to the drains of the MOSFETs 105 and 106. For using the memory cell as the RAM, the contact 107 or a FET 105 is connected to the contact 111 of the contact point N1 of the FF, and the contact 108 of an FET 106 to the contact 112 of the contact point N2 of the FF. Thus, the RAM with one bit can be generated. Respective ROMs of one bit are generated according to whether the contacts 107 and 108 are connected to contacts 109 and 110 connected to the earth. Consequently, one memory cell can be set to the RAM with one bit or in the ROM with two bits.


Inventors:
YASUI TAKASHI
TSUKAGOSHI TOSHIHIRO
Application Number:
JP1105887A
Publication Date:
July 21, 1988
Filing Date:
January 19, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
RICOH KK
International Classes:
H01L27/118; G11C11/34; G11C11/41; H01L21/82; H01L21/822; H01L21/8244; H01L27/04; H01L27/10; H01L27/11; (IPC1-7): G11C11/34; H01L21/82; H01L27/04; H01L27/10
Domestic Patent References:
JPS57166032A1982-10-13
JP58128441B
JP60176550B
JPS55160392A1980-12-13
JPS60134435A1985-07-17
Attorney, Agent or Firm:
Aoyama Aoi



 
Previous Patent: JPS63177394

Next Patent: JPS63177396