Title:
GATE ARRAY TESTING METHOD
Document Type and Number:
Japanese Patent JP2000137060
Kind Code:
A
Abstract:
To test reliability for a gate array using many transistors as much as possible, pursuant to a method close to an LSI operation.
A large scale ring oscillator 2 is formed on a gate array master chip 1 using a large majority of transistors out of all the transistors in a gate array, and the ring oscillator 2 is self-oscillated to detect its generated frequency. Metal layers 3, 4 for constituting the large scale ring oscillator 2 are wired to be near to the gate array, and the gate array master chip 1 is set in a package of the gate array to be tested.
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Inventors:
FUNAKI MASANORI
NAKANISHI SATORU
MONJUJI HIROAKI
NAKANISHI SATORU
MONJUJI HIROAKI
Application Number:
JP32600598A
Publication Date:
May 16, 2000
Filing Date:
October 30, 1998
Export Citation:
Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
G01R31/26; G01R31/28; G01R31/317; H01L21/82; H01L27/118; (IPC1-7): G01R31/317; G01R31/26; G01R31/28; H01L21/82; H01L27/118
Attorney, Agent or Firm:
Nihei Masataka
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