To reduce power consumption without enlarging skew by distributing registers to plural partial trees, so that the number of the same registers becomes large in a register transfer condition, forming a clock tree and setting the enable logic of the partial trees, where the registers are distributed to be the sum set of the register transfer condition of respective clusters.
A clock tree is formed as the set of partial trees T0 to T4. A clock CLK is inputted to one input of AND elements G0 to G4 through a buffer 11. Enable logics En(T9) to En(T4) controlling the opening/closing of the AND elements are inputted to the other input terminal of the elements. When the enable logics are realized, the clock CLK is supplied to the partial trees T0 to T4 through the AND elements. When the AND elements G0 to G4 are gated, the enable logic becomes OR of the register transfer condition of a register group allocated to the partial tree.
KITAHARA TAKESHI
USAMI MASAYOSHI
