Title:
GENERATOR CIRCUIT FOR JITTER-LESS PULSE SIGNAL
Document Type and Number:
Japanese Patent JPS5436125
Kind Code:
A
Abstract:
PURPOSE: To prevent the jitter in the output of the counter by the simultaneous generation of the clock and reset, by using the clock pulse being the count input as a plurality of clock pulses having different phases with selection.
Inventors:
ISHIMARU NOBUYUKI
Application Number:
JP10174377A
Publication Date:
March 16, 1979
Filing Date:
August 26, 1977
Export Citation:
Assignee:
HITACHI ELECTRONICS
International Classes:
H04N5/04; H04N5/06; H04N5/073; (IPC1-7): H04N5/04; H04N5/06