Title:
GLOBAL DATA LAYOUT OPTIMIZING METHOD
Document Type and Number:
Japanese Patent JP3628718
Kind Code:
B2
Abstract:
PURPOSE: To realize an optimum data layout and to improve the performance by automatically laying out data at the time of performing the parallel operation in distributed memory type parallel computers.
CONSTITUTION: When plural processors PE0 and PE1 are provided and data layout is distributed and allocated to respective processors through a communication network 3 to perform the parallel processing, a host computer 1 changes the execution order of programs if meanings of programs are not changed though the execution order is so changed that codes of DO loops having the same desirable data layout are continuous. When two or more processing loops are different by desirable data layouts in the case of accessing the same array in two or more dimensions, the parallel operation is performed based on profile information in accordance with the desirable data layout of the loop having the largest influence upon the performance.
Inventors:
Tatsuya Shindo
Application Number:
JP4762194A
Publication Date:
March 16, 2005
Filing Date:
March 18, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F15/16; G06F9/45; G06F9/50; G06F15/80; (IPC1-7): G06F15/80; G06F9/45; G06F9/50
Domestic Patent References:
| JP6231099A | ||||
| JP7141198A | ||||
| JP3091035A |
Attorney, Agent or Firm:
Tatsuo Imamura
Akira Yamatani
Akira Yamatani