Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
GOLD ELECTRODE MULTILAYER INTERCONNECTION STRUCTURE
Document Type and Number:
Japanese Patent JPH02125446
Kind Code:
A
Abstract:

PURPOSE: To reduce the contact resistance of metal interconnections passing through an interlayer insulating film smoothly on the side face of a metal layer by forming the layer of the lowermost of second interconnection electrode in contact with gold of the upper layer metal of first interconnection electrode nearer to a semiconductor substrate side with a material scarcely chemically reacting with gold and having satisfactory adhering to an interlayer insulating film.

CONSTITUTION: A Pt-Ti metal film of base metal is removed by selectively etching in the mask pattern of metal layer of gold of an uppermost layer to form a first wiring electrode 3. Then, an interlayer insulating film 4 is formed on the electrode 3. A photoresist layer is formed thereon, a window is opened thereat, and a hole is opened in the film 4 by etching. Then, the photoresist layer is removed, and a TiN layer, a Pt layer are sequentially formed thereon. Thereafter, the TiN-Pt metal film is coated with a predetermined mask pattern, and gold plated. Subsequently, the mask pattern is removed, the remaining Ti-Pt film is removed, and a second interconnection electrode 6 made of metal layer of TiN-Pt-Al and a through hole 5 are formed.


Inventors:
TSUDA HIROSHI
Application Number:
JP27885588A
Publication Date:
May 14, 1990
Filing Date:
November 02, 1988
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H01L23/52; H01L21/28; H01L21/3205; H01L21/768; H01L23/522; H01L29/43; (IPC1-7): H01L21/3205; H01L21/90; H01L29/46
Domestic Patent References:
JPS59139647A1984-08-10
JPS62144355A1987-06-27
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
Previous Patent: JPH02125445

Next Patent: JPH02125447