PURPOSE: To shorten the event processing time in the simulation of a large-scale integrated circuit by connecting in parallel the register groups which are connected to a main memory via an address bus and a data bus.

CONSTITUTION: Four parallel register groups formed by storing a microcode list pointer, an address, a value address and a value repacement word number in registers RG respectively is called an even unit. Then an optional even number of event units are connected in parallel. The registers RG are connected in parallel in the number of (number of even units)/2 to form a parallel RG group 1. The (number of event units)/2 pieces of value replacement comparator 2 consisting of an addition counter, a subtraction counter and a comparator are provided. The circuit 2 and the RG group 1 are connected to a main memory 3 via a data bus 4 and an address bus 5. Furthermore a hardware imprinter device 7 is connected to the RG group 1 via the bus 4. The RG group 1 undergoes the parallel processing with the timing produced from a timing control circuit 6. Then an access is given to the memory 3.