PURPOSE: To realize a hierarchical design method realizing intersection of wirings which is one time less than the number of wiring layers, without changing the wiring layers, by recognizing leading-out terminals to the outside, and enabling wiring of all wiring layers.

CONSTITUTION: In the logic design, symbols 2 and signal leading-out terminals 3 are arranged in the range of a sheet 1, the symbols 2 are connected with terminals of the signal leading-out terminals 3 by using wires 5, the wires 5 are shown by net names 6, and proper names 8 of symbols for outer I/O use are defined to be identical to the names 9 of signal leading-out terminals. In the layout design, cells 18 are arranged in the range of an outer cell 17, and electrically connected with terminals 20 by using wirings 19. When a wiring layer is to be changed, a hole 21 is formed between wiring layers, and the wiring is made to pass through the hole, thereby enabling the change of the wiring layer. Hence when the number of wiring layers is N by signal terminals 22 constituted of all wiring layers, at least (N-1) times cross wiring are possible without changing wiring layers, so that an integrated circuit device can be miniaturized.