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Title:
高性能、フレキシブル、かつコンパクトな低密度パリティ検査(LDPC)コード
Document Type and Number:
Japanese Patent JP7050853
Kind Code:
B2
Abstract:
Certain aspects of the present disclosure can enable low-density parity-check, LDPC, code designs to support large ranges of rates, blocklengths, and granularity. Thereby, a method is disclosed comprising determining a low-density parity-check, LDPC, code base graph associated with a plurality of LDPC codes for a plurality of code rates and blocklengths, the LDPC base graph having a number of base graph columns corresponding to a maximum number of base information bits, determining a lifting size value for generating a lifted LDPC parity check matrix, PCM, generating the lifted LDPC PCM based on the base graph and the lifting size value, and generating an LDPC code based on the lifted LDPC PCM and an all zero matrix, wherein the LDPC code was shortened by either (i) removing one or more of the base graph columns or (ii) removing one or more lifted LDPC PCM columns, and wherein the shortening was based on at least one of: a desired code rate, lifting size value, or blocklength for a transmission.

Inventors:
Thomas Joseph Richardson
Shrinivas Decal
Application Number:
JP2020092262A
Publication Date:
April 08, 2022
Filing Date:
May 27, 2020
Export Citation:
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Assignee:
Qualcomm, Inc.
International Classes:
H03M13/19; H04L1/18
Domestic Patent References:
JP2010517444A
JP6749427B2
JP2016507200A
Foreign References:
US20110047433
US20110239075
Other References:
Tom Richardson, et al.,LDPC Proposal Update,3GPP2-Drafts, C30-20061218-004,2006年12月18日
Min-seok Oh, et al.,LDPC Coding for OFDMA PHY, IEEE C802.16e-04/487r3,2004年11月
Intel Corporation,LDPC code design for NR[online], 3GPP TSG-RAN WG1#85 R1-164183,2016年05月
Qualcomm Incorporated,LDPC Design Overview[online], 3GPP TSG-RAN WG1#85 R1-164697,2016年05月
Attorney, Agent or Firm:
Murayama Yasuhiko
Shinpei Kuroda



 
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