Title:
HIGHLY INTEGRATED DRAM DEVICE, AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3810863
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce stringer or bridge phenomena, and secure lineup margin in etching process for formation of a BC for a storage node, and improve the problem of etching stoppage by performing the BC process for connection with a storage electrode in advance before patterning a bit line in a DRAM cell.
SOLUTION: A contact hole to expose a source region 118 between gates is made by dry-etching the fifth insulating layer 136 and the second and first interlayer insulating layers 135 and 125, using a prescribed mask pattern, after depositing the fifth insulating layer 136 all over the flattened second interlayer insulating film 135. A plugging bar 140 to connect with a source region 118 is made by the third flattening process after stopping the contact hole with the forth conductive material. After being connected with the storage electrode, a bit line 150 is made, and it is connected to a pad 130. Hereby, the etching stop problem in BC process and the security problems of process margin such as lineup margin, etc., can be improved.
Inventors:
Lee Keisuke
Application Number:
JP15569896A
Publication Date:
August 16, 2006
Filing Date:
June 17, 1996
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/8242; H01L27/04; H01L21/822; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242; H01L27/04; H01L21/822
Domestic Patent References:
| JP6085086A | ||||
| JP7066300A | ||||
| JP3297166A | ||||
| JP5136369A |
Attorney, Agent or Firm:
Masaki Hattori