Title:
ハウジング収容型半導体デバイス
Document Type and Number:
Japanese Patent JP7428412
Kind Code:
B2
Abstract:
Packaged semiconductor device having a heat sink, wherein the heat sink has a top, a bottom, lateral surfaces that connect the top to the bottom, and, extending within the heat sink, a cooling structure with an inlet line as well as an outlet line for a cooling medium, and is composed of an electrically conductive material with a first coefficient of thermal expansion at the top and with a second coefficient of thermal expansion at the bottom, a die is arranged on each of the top and the bottom of the heat sink and is connected to the heat sink in an electrically conductive manner, the coefficients of thermal expansion of the top and of the bottom of the heat sink correspond in each case to the coefficient of thermal expansion of the die arranged thereon or differ from the coefficient of thermal expansion of the die arranged thereon by at most 10% or by at most 20%.
Inventors:
Jens Kowalski
Application Number:
JP2022066976A
Publication Date:
February 06, 2024
Filing Date:
April 14, 2022
Export Citation:
Assignee:
3-5 Power Electronics GmbH
International Classes:
H01L23/473; H01L23/34
Domestic Patent References:
| JP2001332679A | ||||
| JP2006303290A | ||||
| JP2002270748A | ||||
| JP2009022107A |
Foreign References:
| US20020186545 | ||||
| WO2015086184A1 | ||||
| CN101345469A |
Attorney, Agent or Firm:
Einzel Felix-Reinhard
Taku Morita
Junichi Maekawa
Hideo Nagashima
Ueshima class
Taku Morita
Junichi Maekawa
Hideo Nagashima
Ueshima class
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