To provide a method for designing a semiconductor integrated circuit in the consideration of a variation in a logic composition process.

The method for designing the semiconductor integrated circuit includes steps of: specifying a variation value as a numerical value showing the variation of the delay time of cells; generating a netlist by a logic composition from circuit description; calculating a variation total by totaling variation values of cells configuring each of a plurality of paths reaching the input edge of a flip flop under consideration in the netlist; selecting the maximum value of the variation totals of the plurality of paths as a maximum variation total; selecting the worst value of timing slacks of the plurality of paths as the worst timing slack; and exchanging the cells of the netlist so that the maximum variation total can be decreased in a range in which the worst timing slack can be prevented from being worse than a predetermined slack value.

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