Title:
キャッシュメモリをメインメモリに同期させる方法
Document Type and Number:
Japanese Patent JP4047281
Kind Code:
B2
Abstract:
Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.
Inventors:
Gummel, Bernd M.
Kunemund, Thomas
Zetlark, Holger
Kunemund, Thomas
Zetlark, Holger
Application Number:
JP2003550068A
Publication Date:
February 13, 2008
Filing Date:
October 31, 2002
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G06F12/0804; G06F12/14; G06F21/60; G06F21/62; H04L9/10
Domestic Patent References:
| JP3214245A | ||||
| JP9258977A | ||||
| JP2003051819A | ||||
| JP2002140236A | ||||
| JP54083329A |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita