METHOD OF VERIFYING CHIP, DEVICE, ELECTRONIC DEVICE, COMPUTER READABLE STORAGE MEDIUM, AND COMPUTER PROGRAM

Title:

METHOD OF VERIFYING CHIP, DEVICE, ELECTRONIC DEVICE, COMPUTER READABLE STORAGE MEDIUM, AND COMPUTER PROGRAM

Document Type and Number:

Japanese Patent JP2022036889

Kind Code:

A

Abstract:

To provide a method of verifying a chip for use in artificial intelligence chip design, simulator development and function verification, a device, an electronic device, a storage medium, and a computer program.SOLUTION: A method of verifying a chip includes: arranging a software environment and a hardware environment generated on the basis of a chip and associated with the chip via a profile containing a plurality of commands and data required for executing the plurality of commands; executing the plurality of commands in each of the software environment and the hardware environment; acquiring first information generated by executing the plurality of commands in the software environment and second information generated by executing the plurality of commands in the hardware environment; and verifying the chip on the basis of the first and second information generated. Each of the first information and the second information contains the plurality of commands executed, addresses of the plurality of commands executed, and the data generated by executing the plurality of commands.SELECTED DRAWING: Figure 2

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Inventors:

ZHAO BAOFU
DU XUELIANG
LIU JIAQIANG
HUANG ZITENG

Application Number:

JP2021060825A

Publication Date:

March 08, 2022

Filing Date:

March 31, 2021

Export Citation:

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Assignee:

BEIJING BAIDU NETCOM SCI & TECH CO LTD
KUNLUNXIN TECH BEIJING CO LTD

International Classes:

G06F30/3308; G06F11/36

Foreign References:

WO2002063473A1	2002-08-15
WO2006008721A2	2006-01-26
US20050076282A1	2005-04-07

Attorney, Agent or Firm:

Hideki Miyata
Hiroaki Sakai

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