Title:
【発明の名称】自己並列化式のコンピュータ・システムおよび方法
Document Type and Number:
Japanese Patent JP2898820
Kind Code:
B2
Abstract:
A self-parallelizing computer system and method asynchronously processes execution sequences of instructions in two modes of execution on a set of processing elements which communicate with each other. Each processing element is capable of decoding instructions, generating memory operand addresses, executing instructions and referencing and updating its own set of general purpose registers. These processing elements act in concert during the first mode of execution not only to execute the instructions in an execution sequence but also to partition an execution sequence into separate instruction subsequences. The separate instruction subsequences are stored along with additional information which will allow the stored subsequences to be correctly executed in parallel. Subsequent re-execution of the same execution sequence is done much faster in the second mode of execution, since each of the processing elements decodes and executes only the instructions in one of the subsequences while the other processing elements are concurrently each doing the same with another one of the subsequences.
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Inventors:
RUDORUFU NEISAN REHITOSHATSUFUEN
KATSUTAMURI EEKANADAMU
KATSUTAMURI EEKANADAMU
Application Number:
JP15909292A
Publication Date:
June 02, 1999
Filing Date:
June 18, 1992
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F9/38; G06F9/44; G06F15/16; G06F15/177; (IPC1-7): G06F15/16
Domestic Patent References:
| JP3119428A |
Other References:
ＣＯＭＰＣＯＮ’８７，ＩＥＥＥ，ｐ．１７７−１８０，（１９８７），Ｊ．Ａ．ＦＩＳＨＥＲ，”Ａ ＮＥＷ ＡＲＣＨＩＴＥＣＴＵＲＥ ＦＯＲ ＳＵＰＥＲＣＯＭＰＵＴＩＮＧ”
ＳＵＰＥＲＣＯＭＰＵＴＥＲＳ：ＤＥＳＩＧＮ ＡＮＤ ＡＰＰＬＩＣＡＴＩＯＮＳ，ｐ．１８６−２０３，（１９８４），Ｊ．Ｒ．ＡＬＬＥＮ 外，”ＰＦＣ：Ａ ｐｒｏｇｒａｍ ｔｏ ｃｏｎｖｅｒｔ ｆｏｒｔｒａｎ ｔｏ ｐａｒａｌｌｅｌ ｆｏｒｍ”
ＳＵＰＥＲＣＯＭＰＵＴＥＲＳ：ＤＥＳＩＧＮ ＡＮＤ ＡＰＰＬＩＣＡＴＩＯＮＳ，ｐ．１８６−２０３，（１９８４），Ｊ．Ｒ．ＡＬＬＥＮ 外，”ＰＦＣ：Ａ ｐｒｏｇｒａｍ ｔｏ ｃｏｎｖｅｒｔ ｆｏｒｔｒａｎ ｔｏ ｐａｒａｌｌｅｌ ｆｏｒｍ”
Attorney, Agent or Firm:
Jiro Yamamoto (3 outside)