【発明の名称】ADC用の電流-電圧積分器

Japanese Patent JP3464228

B2

An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise. In the described embodiment, a correlated double sampling capacitor is discharged to zero while the integrating capacitor is precharged and kT/C error and charge injection error voltages of opposite polarity are stored on both the integrating capacitor and the correlated double sampling capacitor. The correlated double sampling capacitor is switched into the feedback of the operational amplifier in series with the integrating capacitor to automatically cancel the error voltages and present a more accurate input to the delta-sigma analog-to-digital converter.

Karthof, Timothy Buoy
James Elle, Tadsen

JP54304498A

November 05, 2003

April 06, 1998

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BURR-BROWN CORPORATION

G06G7/186; H03M1/12; (IPC1-7): H03M1/12; G06G7/186

JP5421340A

【文献】米国特許4988900(US,A)
【文献】米国特許4393351(US,A)

Kazuo Shamoto (4 outside)

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