Title:
【発明の名称】書込み雑乱に対する向上した耐性を持つフローティングゲートメモリアレイデバイス
Document Type and Number:
Japanese Patent JPH07507176
Kind Code:
A
Abstract:
An electrically programmable and erasable floating gate memory array device is disclosed. The array has a plurality of column address lines, a plurality of row address lines, and a plurality of common source lines. Each of the memory cells has one terminal connected to one of the column address lines, another one connected to one of the row address lines, and a third connected to one of the common source lines. By appropriate selection circuit, a high voltage source can be connected to either the row address line to effect erasure of charges on the floating gate of the memory cells connected to the selected row address line or to the common source line to selectively program the memory cells connected to the associated common source line. In this manner, write disturbance can be limited.
Inventors:
Genk, Qin S.
One, pin
One, pin
Application Number:
JP51574293A
Publication Date:
August 03, 1995
Filing Date:
February 24, 1993
Export Citation:
Assignee:
Silane Storage Technology, Inc.
International Classes:
G11C17/00; G11C16/02; G11C16/04; G11C16/08; G11C16/12; G11C16/14; G11C16/16; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/06; G11C16/02; G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)