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Title:
【発明の名称】シリコン上に集積された多層強誘電体セルおよびペロブスカイト電子へテロ構造
Document Type and Number:
Japanese Patent JP3373525
Kind Code:
B2
Abstract:
A ferroelectric cell in which a ferroelectric stack of a perovskite ferroelectric sandwiched by cubic perovskite metal-oxide conductive electrodes are formed over a silicon body, such as a polysilicon plug penetrating a field oxide over a silicon transistor. According to the invention, an oxidation barrier is placed between the lower metal-oxide electrode and the polysilicon. The oxidation barrier may be: (1) a refractory metal sandwiched between two platinum layer which forms a refractory oxide in a platinum matrix; (2) an intermetallic barrier beneath a platinum electrode, e.g., of NiAl; or (3) a combination of Ru and SrRuO3 or similar materials. Thereby, the polysilicon plug is protected from oxidation.

Inventors:
Ramesh, Rama Moore Sea
Application Number:
JP50450097A
Publication Date:
February 04, 2003
Filing Date:
June 24, 1996
Export Citation:
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Assignee:
Telcordia Technologies, Inc.
International Classes:
H01B12/00; H01L21/8247; H01L21/02; H01L21/8242; H01L21/8246; H01L27/06; H01L27/10; H01L27/105; H01L27/108; H01L29/788; H01L29/792; (IPC1-7): H01L27/105
Domestic Patent References:
JP492468A
JP793969A
JP774313A
JP6326250A
JP77137A
JP668529A
JP5275711A
JP7504784A
Other References:
【文献】米国特許5270298(US,A)
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)



 
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