Title:
【発明の名称】半導体試験装置のパターンシーケンス制御回路
Document Type and Number:
Japanese Patent JP2915912
Kind Code:
B2
Abstract:
PURPOSE:To form a multiple loop hardly changing the hardware scale by providing a 1st memory, a 2nd memory, a multiplexer, and a counter. CONSTITUTION:The 1st memory 21 is stored with the initial value of each loop in the address corresponding to the loop from a bus 11. The 2nd memory 22 is stored with the number of times in the middle of each loop in the address corresponding to the loop. The read outputs of the memories 21 and 22 are selected by the multiplexer 23 and set in the counter 24. The counting contents of the counter 24 are stored as the halfway number of times of the loop in the loop-corresponding address of the memory 22 through a latch 25. A memory controller 26 controls the selection of write addresses of the memories 21 and 22 and the selection by the multiplexer 23. Consequently, when there are plural loop counters because of the two memories and one counter, similar operation is performed and the control over memory addresses is increased by only one bit to obtain the same effect as the doubling of the number of loop counters.
Inventors:
KAWASAKI KUNIHIKO
IMADA HIDEAKI
IMADA HIDEAKI
Application Number:
JP17297388A
Publication Date:
July 05, 1999
Filing Date:
July 11, 1988
Export Citation:
Assignee:
ADOBANTESUTO KK
International Classes:
G01R31/28; G11C29/00; G11C29/10; G01R31/3183; (IPC1-7): G01R31/3183; G11C29/00
Domestic Patent References:
| JP5914840B2 |
Attorney, Agent or Firm:
Kusano Takashi