Title:
【発明の名称】半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP2802455
Kind Code:
B2
Abstract:
In a semiconductor device, a first conductive interconnection layer and a second conductive interconnection layer are formed respectively on a lower surface and a higher surface of an interlayer insulation film interposing a step-like portion therebetween by employing different photolithography and etching. A dummy interconnection is provided directly beneath the second conductive interconnection layer in the vicinity of the step-like portion. The first and second conductive interconnection layers and are electrically connected to each other by a conductive layer formed directly on the dummy interconnection in a region including the step-like portion to extend over the surface of a silicon substrate. Consequently, even if the step-like portion is larger than depth of focus, the first and second conductive interconnection layers are precisely patterned within depth of focus.
Inventors:
Kaoru Honnami
Application Number:
JP10571991A
Publication Date:
September 24, 1998
Filing Date:
May 10, 1991
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/768; H01L21/8242; H01L27/10; H01L27/108; H01L29/417; (IPC1-7): H01L27/108; H01L21/768; H01L21/8242
Domestic Patent References:
| JP4321213A | ||||
| JP61194771A | ||||
| JP382077A | ||||
| JP6481358A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)