Title:
DATA PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPH0628256
Kind Code:
A
Abstract:
PURPOSE: To provide a cache controller which end user can add to existing microprocessor.
CONSTITUTION: The cache controller 10 is arranged in parallel with microprocessor busses 14, 15, and 29 so as not to hinder the response of a system at the time of a cache miss. A tag RAM 24 of the cache controller 10 has a 2-way constitution, and each way includes a tag bit/effective bit storage part which is used for associative search of a directory to obtain an address of a cache data array. An external cache memory 8 is so constituted that both routes can be used for plural usable modules of the system to execute the route access in parallel with tag look-up.
Inventors:
JIYON HAWAADO KUROOFUOODO
SANDARABUARAZAN RAJIYAGOPARAN
JIEIMUZU NEIDEA
SANDARABUARAZAN RAJIYAGOPARAN
JIEIMUZU NEIDEA
Application Number:
JP33792991A
Publication Date:
February 04, 1994
Filing Date:
November 28, 1991
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Masaki Yamakawa
Next Patent: 半導体製造装置