Title:
【発明の名称】余剰ニューロン決定処理方式
Document Type and Number:
Japanese Patent JP2877413
Kind Code:
B2
Abstract:
PURPOSE:To increase an arithmetic processing speed and to reduce the number of hardwares by specifying unactivated excess neurons in network structure. CONSTITUTION:When a read distance from the zero value of an internal state value of input side internal connection is close to the zero value, the 1st excess neuron specifying means 33 determines that the neuron is an inactive excess neuron which does not respond to an input. When a read distance from the zero value of the internal state value of output side internal connection is close to the zero value, the neuron is determined as an inactive excess neuron which does not generate an output. An excess neuron output means 39 outputs the ID of the determined excess neuron. Consequently, which is the inactivated excess neuron in the network structure part 11 of a network constitution data processor 10 can be specified, the arithmetic processing speed can be increased and the number of hardwares can be reduced.
Inventors:
MASUOKA RYUSUKE
WATABE NOBUO
KAWAMURA AKIRA
OOWADA ARIMICHI
ASAKAWA KAZUO
WATABE NOBUO
KAWAMURA AKIRA
OOWADA ARIMICHI
ASAKAWA KAZUO
Application Number:
JP2627790A
Publication Date:
March 31, 1999
Filing Date:
February 06, 1990
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G06G7/60; G06F15/18; G06N3/02; G06N3/04; G06N99/00; (IPC1-7): G06F15/18
Domestic Patent References:
| JP2231670A | ||||
| JP383157A | ||||
| JP383156A |
Other References:
萩原 将文，中川 正雄，「淘汰機能を有するバックプロパゲーション−Ｌｏｃａｌ Ｍｉｎｉｍｕｍからの回避アルゴリズム−」，電子情報通信学会春季全国大会（１９８９年），Ｐ．７−１９
Attorney, Agent or Firm:
Mitsuyoshi Okada (3 outside)