Title:
【発明の名称】対数検出器を有する装置
Document Type and Number:
Japanese Patent JP3330158
Kind Code:
B2
Abstract:
An apparatus with a logarithmic detector performs the following operations: receiving an input voltage (10), generating a series of subsequently amplified versions (12, 14..20) of the input voltage, rectifying the versions (22, 24...30), thereupon rescaling and converting the versions into currents (32,34...,40), summing the currents and applying the summed current to a resistor (58). With regard to the prior art the order of rectification and rescaling has been interchanged. As a result, the design is simplified, the circuit's supply voltage is lower than that of the prior art, and the circuit is more accurate and easier to compensate for temperature dependence.
Inventors:
Ali Photo Watt-Ahmadi
Naslorer Saede Navid
Naslorer Saede Navid
Application Number:
JP14289692A
Publication Date:
September 30, 2002
Filing Date:
June 03, 1992
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G06G7/24; H03G3/30; H03G7/00; H03G7/06; (IPC1-7): G06G7/24; H03G3/30
Other References:
【文献】米国特許4990803(US,A)
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)