Title:
【発明の名称】回路模擬試験装置及び該装置における半導体集積回路の試験方法
Document Type and Number:
Japanese Patent JP2839938
Kind Code:
B2
Abstract:
PURPOSE:To improve the test accuracy by providing a 2nd data processing means which supplies analog test data to the semiconductor device to be tested and a 1st data processing means which compares the simulation test result data of the 2nd data processing means with expected value data of the semiconductor device to be tested. CONSTITUTION:Logical test data D2 is generated according to test pattern data D1 of the semiconductor device 16 to be tested, a 1st simulation test process regarding the digital circuit of the semiconductor device 16 to be tested is performed according to the logical test data D1, and analog test data D3 is generated according to the logical test data D2 of the semiconductor device to be tested. Further, a 2nd simulation test process regarding the analog circuit of the semiconductor device 16 to be tested is performed according to the analog test data D3 and then the semiconductor device 16 to be tested is decided according to test result data D51 and D52 obtained by the 1st and 2nd simulation test processes. Consequently, the test accuracy is improved.
Inventors:
SEGAWA JUJI
MIZUTANI TOORU
GOTO KUNIHIKO
MIZUTANI TOORU
GOTO KUNIHIKO
Application Number:
JP16926990A
Publication Date:
December 24, 1998
Filing Date:
June 27, 1990
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G01R31/316; G06F17/50; G06G7/48; G01R31/28; (IPC1-7): G01R31/28; G01R31/316
Domestic Patent References:
| JP62242872A | ||||
| JP61234377A | ||||
| JP5797466A |
Attorney, Agent or Firm:
Keizo Okamoto