Title:
【発明の名称】しきい値素子の設計方法およびその方法で設計可能なしきい値素子
Document Type and Number:
Japanese Patent JP3315641
Kind Code:
B2
Abstract:
A threshold element is implemented by output wired CMOS circuit. The corresponding threshold function is transformed to a form including the ratio of beta values of n- and p-transistors. Inputs are allocated to the n- and p-transistors in accordance with the ratio. The logic circuitry can be implemented with half of transistors in the similar implementation in a conventional CMOS circuitry, since every character entry corresponds to a single transistor.
Inventors:
Victor I Bershawski
Application Number:
JP5407998A
Publication Date:
August 19, 2002
Filing Date:
January 30, 1998
Export Citation:
Assignee:
Monolith Co., Ltd.
International Classes:
G06F15/18; G06F7/50; G06F7/501; G06G7/60; G06N3/063; H01L21/8238; H01L27/092; H03K19/08; H03K19/20; (IPC1-7): H01L21/8238; G06F15/18; G06G7/60; H01L27/092; H03K19/20
Domestic Patent References:
| JP7262292A | ||||
| JP10177612A | ||||
| JP9237307A |
Attorney, Agent or Firm:
Kenki Morishita