PURPOSE: To provide the interruption control circuit for a data transfer device unnecessitating processing such as register save/recovery and control table address translation or the like corresponding to an input/output device.

CONSTITUTION: When interruption is generated from the input/output device, the interruption display bit of an interruption register 31 is turned on, an interruption request detection signal is turned on by an interruption request detection circuit 32, and an interruption number generation circuit 33 generates an interruption number from the contents of the interruption display bit. A base address preparation circuit 35 calculates a base address from this interruption number and the number of registers previously set to a register number register 34, and a register address preparation circuit 37 generates the physical address of the register by adding the base address and the register number of an instruction register 38.